Foundry: 4 nm chip production at TSMC already in preparation

TSMC officially planned only with the 3 nm chip production for 2022.

The largest contract manufacturer in the semiconductor industry, TSMC, is expected to have made further improvements to the N5 and to have already prepared the N4 expected for 2022. Nodes N4 and N3 are expected to follow an optimized plus variant of the N5 from the year after next.

N5P with 20 percent more power than N7

According to media reports, TSMC has achieved significant improvements in 5 nm production and will offer a 5 nm plus technology as an optimized Finfet variant under the name "N5P". Until then, however, it may still take a little time, the first test phase for production in the N5P process is to take place in the first quarter of 2021. According to Digitimes, the N5P should provide about 20 percent more power or 40 percent less power consumption than the current N7 process.

However, the regular N5 process is already predicted to produce up to 15 percent more power or 30 percent less energy than N7, so from N5 to N5P the step would be significantly smaller and ultimately something like current from N7 to N7P.

New N4 process from 2023

To surprise, TSMC explained that preparations for the production of the new node N4 have begun. TSMC officially planned only with the 3 nm chip production for 2022. According to the magazine Eetimes, which quotes TSMC Board member Mark Liu, N5P will also appear in 2022, N4 in 2023. The processes will therefore complement existing ones and fill any gaps.

N4 is an evolution from N5.We are already in business negotiations with customers on N4.

TSMC generally gives no information about customers, but one is already in negotiations. At the top are probably the usual suspects, especially Apple and Qualcomm from the mobile sector, AMD, Nvidia and others from the PC business.

Samsung to manufacture first 3 nm chips in 2021

The Samsung Foundry also wants to produce 3 nanometres of chips in 2021 and already announced in May 2019 that it has laid the first design guidelines for what is probably the largest manufacturing step in many years. The gate-all-around technology is to be used for the first time at 3 nm.